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order number: 248989, revision: 003 31-oct-2005 intel ? lxt914 flexible quad ethernet repeater datasheet the intel ? lxt914 flexible quad ethernet repeater (called hereafter the lxt914 repeater) is an integrated multi-port repeater designed for mixed-media networks. it provides all the active circuitry required for the repeater function in a single cmos device. it includes one attachment unit interface (aui) port and four 10base-t transceivers. the aui port is mode selectable: dte mode allows connection of an external transceiver (10base2, 10base5, 10base-t or foirl) or a drop cable. mau mode creates a mau output allowing direct connection to another dte interface. the 10base-t transceivers are entirely self-contained with internal filters which simplify the design work required for fcc-compliant emi performance. an inter-repeater backplane interface allows 128 or more 10base-t ports to be cascaded together. in addition, a serial port provides information for network management. the lxt914 repeater requires only a single 5-volt power supply due to an advanced cmos fabrication process. product features applications four integrated 10base-t transceivers and one aui transceiver on a single chip programmable dte/mau interface on aui port seven integrated led drivers with four unique operational modes on-chip transmit and receive filtering automatic partitioning of faulty ports, enabled on an individual port basis automatic polarity detection and correction programmable squelch level allows extended range in low-noise environments synchronous or asynchronous inter- repeater backplane supports ?hot swapping? inter-repeater backplane allows cascaded repeaters, linking 128 or more 10base-t ports serial port for selecting programmable options 68-pin plcc (commercial or extended temp range) 100-pin pqfp (commercial temp range) lan repeaters integrated repeaters switched repeater clusters
31-oct-2005 datasheet intel ? lxt914 flexible quad ethernet repeater 2 order number: 248989, revision: 003 legal lines and disclaimers information in this document is provided in connection with intel? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. intel may make changes to specifications and product descriptions at any time, without notice. intel corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property right s that relate to the presented subject matter. the furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. the intel ? lxt914 flexible quad ethernet repeater may contain design defects or errors known as errata which may cause the product to dev iate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an order number and are referenced in this document, or other intel literature may be obtained b y calling 1-800-548-4725 or by visiting intel's website at http://www.intel.com . intel and the intel logo are trademarks or registered trademarks of intel corporation or its subsidiaries in the united states and other countries. *other names and brands may be claimed as the property of others. copyright ? 2005, intel corporation. all rights reserved.
intel ? lxt914 flexible quad ethernet repeater datasheet 31-oct-2005 intel ? lxt914 flexible quad ethernet repeater order number: 248989, revision: 003 3 contents 1.0 lxt914 pin assignments and signal descriptions ....................................................................7 2.0 functional description ................................................................................................................14 2.1 introduction ................................................................................................................ .........14 2.2 external interfaces......................................................................................................... ..... 14 2.2.1 10base-t ports ....................................................................................................14 2.2.2 aui port .................................................................................................................1 4 2.2.3 serial port ..............................................................................................................1 4 2.2.4 inter-repeater backplane ......................................................................................15 2.2.4.1 synchronous irb operation ..................................................................15 2.2.4.2 asynchronous irb operation ................................................................ 15 2.3 internal repeater circuitry................................................................................................. .15 2.4 initialization .............................................................................................................. ...........16 2.4.1 local management mode initialization ..................................................................16 2.4.2 external management mode initialization .............................................................. 19 2.5 10base-t port operation ..................................................................................................20 2.5.1 10base-t reception.............................................................................................20 2.5.1.1 programmable internal squelch level................................................... 21 2.5.1.2 polarity detection and correction .......................................................... 21 2.5.2 10base-t transmission .......................................................................................21 2.5.3 10base-t link integrity testing............................................................................21 2.6 aui port operation .......................................................................................................... ... 22 2.6.1 aui reception........................................................................................................22 2.6.2 aui transmission ..................................................................................................22 2.6.3 aui mode selection (dte/mau)............................................................................22 2.7 collision handling .......................................................................................................... .....23 2.8 security mode............................................................................................................... ......23 2.9 led display ................................................................................................................. .......23 3.0 application information ..............................................................................................................27 3.1 layout requirements......................................................................................................... .27 3.1.1 the twisted pair interface .....................................................................................27 3.1.2 the rbias pin.......................................................................................................27 3.2 12-port hub repeater........................................................................................................ .27 3.3 8-port print or file server ................................................................................................. ..28 4.0 test specifications ......................................................................................................................35 5.0 package specifications ...............................................................................................................40 5.1 top-label marking........................................................................................................... ... 42 6.0 product ordering information ....................................................................................................44
intel ? lxt914 flexible quad ethernet repeater 31-oct-2005 datasheet intel ? lxt914 flexible quad ethernet repeater 4 order number: 248989, revision: 003 figures 1 block diagram ................................................................................................................. ............. 7 2 pin assignments............................................................................................................... ............ 8 3 global state machine .......................................................................................................... ....... 17 4 partitioning state machine.................................................................................................... ...... 18 5 integrated led driver indications............................................................................................. .. 26 6 12-port application schematic, 68-pin plcc package (sheet 1 of 4)....................................... 29 7 12-port application schematic, 68-pin plcc package (sheet 2 of 4)....................................... 30 8 12-port application schematic, 68-pin plcc package (sheet 3 of 4)....................................... 31 9 12-port application schematic, 68-pin plcc package (sheet 4 of 4)....................................... 32 10 8-port application schematic, led mode 1 with auisel = mau (sheet 1 of 2) ....................... 33 11 8-port application schematic, led mode 1 with auisel = mau (sheet 2 of 2) ....................... 34 12 serial port timing ........................................................................................................... ............ 38 13 inter-repeater bus timing .................................................................................................... ..... 39 14 lxt914pc/pe package specifications ...................................................................................... 40 15 lxt914qc package specifications ........................................................................................... 41 16 sample plcc package - intel ? lxt914 repeater .................................................................... 42 17 sample pb-free (rohs-compliant) plcc package - intel ? lxt914 repeater ........................ 42 18 sample pqfp package - intel ? lxt914 repeater .................................................................... 43 19 sample pb-free (rohs-compliant) pqfp package - intel ? lxt914 repeater ........................ 43 20 ordering information matrix ? sample........................................................................................ 4 5 tables 1 power, ground, and clock signal descriptions............................................................................ 9 2 inter-repeater backplane signal descriptions ........................................................................... 10 3 mode select and control signal descriptions ............................................................................ 10 4 serial port signal descriptions (external management mode) .................................................. 11 5 serial port signal descriptions (local management mode) ....................................................... 11 6 miscellaneous control signal descriptions ................................................................................ 12 7 led driver signal descriptions ................................................................................................ .. 12 8 repeater port signal descriptions ............................................................................................. 13 9 setup register bit assignments ................................................................................................ .19 10 setup register bit definitions............................................................................................... ......19 11 packet status register bit assignments .................................................................................... 20 12 packet status register bit definitions ....................................................................................... .20 13 aui mode selection (dte/mau) ................................................................................................ 2 2 14 led mode selection ........................................................................................................... ........24 15 mode 0 (default) led truth table ............................................................................................. 24 16 mode 1 led truth table ....................................................................................................... .....24 17 mode 2 led truth table ....................................................................................................... .....25 18 mode 3 led truth table ....................................................................................................... .....25 19 manufacturers magnetics list................................................................................................. ....28 20 absolute maximum ratings..................................................................................................... ... 35 21 recommended operating conditions ........................................................................................ 35 22 i/o electrical characteristics 1 .....................................................................................................35 23 aui electrical characteristics ............................................................................................... ......36 24 twisted-pair electrical characteristics ...................................................................................... .36 25 irb electrical characteristics ............................................................................................... ......37
intel ? lxt914 flexible quad ethernet repeater datasheet 31-oct-2005 intel ? lxt914 flexible quad ethernet repeater order number: 248989, revision: 003 5 26 switching characteristics.................................................................................................... ........37 27 serial port timing?external mode ............................................................................................3 7 28 inter-repeater bus timing.................................................................................................... ......38 29 product ordering information ................................................................................................. ....44
intel ? lxt914 flexible quad ethernet repeater 31-oct-2005 datasheet intel ? lxt914 flexible quad ethernet repeater 6 order number: 248989, revision: 003 revision history date revision description 31-oct-2005 003 ? added section 5.1 and figure 16 through figure 19 (rohs top labels). ? added section 6.0, ?product ordering information? on page 44 with table 29 ?product ordering information? on page 44 and figure 20 ?ordering information matrix ? sample? on page 45 . feb 2001 002 ? added layout requirements section under application information. ? modified i/o electrical characteristics table: change max value under supply current from 180 to 240; add text under test conditions: ?100 test load, no leds?; add table note 3.
intel ? lxt914 flexible quad ethernet repeater datasheet 31-oct-2005 intel ? lxt914 flexible quad ethernet repeater order number: 248989, revision: 003 7 1.0 lxt914 pin assignments and signal descriptions figure 1. block diagram control twisted-pair port #1 tp port #2 f tp port #3 f tp port #4 f aui port (mode selectable dte/mau) repeater (state machine, timing recovery, fifo, etc.) management port (serial i/f) inter-repeater backplane port led drivers filter 4 reset sysclk jm cf aui 4 tp1 - 4 sclk sdo sdi seni seno bclkio irdat ircol ircfs irden irena 4 4 loc/ext a/sync dop don dip din do/di do/di do/di fps/secaui auisel* cin cip din dip don dop * the aui select function is provided on a dedicated auisel pin in the 100-pin pqfp (lxt914qc). in the 68-pin plcc (lxt914pc/pe) the aui select function is provided through shared usage of the jm led pin.
intel ? lxt914 flexible quad ethernet repeater 31-oct-2005 datasheet intel ? lxt914 flexible quad ethernet repeater 8 order number: 248989, revision: 003 figure 2. pin assignments lxt914pc/pe xx xxxxxxxx part # fpo # rev # b5381-01 bsmc xxxxxxxx part # fpo # rev # b5382-01 bsmc
intel ? lxt914 flexible quad ethernet repeater datasheet 31-oct-2005 intel ? lxt914 flexible quad ethernet repeater order number: 248989, revision: 003 9 table 1. power, ground, and clock signal descriptions pin # symbol i/o description plcc pqfp 1 2 3 26 49 55 67 68 ? ? 27 61 62 69 70 88 89 90 91 93 vcc1 vcc2 vcc3 vcc4 vcc5 vcc6 vcc7 vcc8 vcc9 vcc10 ? ? ? ? ? ? ? ? ? ? power supply inputs. these pins each require a +5 vdc power supply. the various pins may be supplied from a single power source, but special de-coupling requirements may apply. each vcc input must be within 0.3 v of every other vcc input. 9 34 36 38 39 46 52 58 ? 39 41 43 44 58 65 66 73 99 gnd1 gnd2 gnd3 gnd4 gnd5 gnd6 gnd7 gnd8 gnd9 ? ? ? ? ? ? ? ? ? ground. these pins provide ground return paths for the various power supply pins. 37 42 rbias ? bias. this pin provides bias current for the internal circuitry. the 100 a bias current is provided through an external 12.4 k resistor to ground. 10 4 bclkio i/o backplane clock. this 10 mhz clock synchronizes multiple repeaters on a common backplane. in the synchronous mode, bclkio must be supplied to all repeaters from a common external source. in the asynchronous mode, bclkio is supplied only when a repeater is outputting data to the bus. each repeater outputs its internally recovered clock when it takes control of the bus. other repeaters on the backplane then sync to bclkio for the duration of the transmission. 11 6 sysclk i system clock. the required 20 mhz system clock is input at this pin. clock must have a 40-60 duty cycle with < 10 ns rise time.
intel ? lxt914 flexible quad ethernet repeater 31-oct-2005 datasheet intel ? lxt914 flexible quad ethernet repeater 10 order number: 248989, revision: 003 table 2. inter-repeater backplane signal descriptions plcc pqfp symbol i/o description 4 94 irena i/o inter-repeater backplane enable. this pin allows individual lxt914 repeaters to take control of the inter-repeater backplane (irb) data bus (irdat). the irena bus must be pulled up locally by a 330 resistor. 1 5 95 irdat i/o irb data. this pin is used to pass data between multiple repeaters on the irb. the irdat bus must be pulled up locally by a 330 resistor. 1 6 96 irden o irb driver enable. the irden pin is used to enable external bus drivers which may be required in synchronous systems with large backplanes. this is an active low signal, maintained for the duration of the data transmission. irden must be pulled up locally by a 330 resistor. 7 8 97 98 ircfs ircol i/o i/o irb collision flag sense (ircfs ) and irb collision (ircol ). these two pins are used for collision signalling between multiple lxt914 devices on the inter-repeater backplane (irb). both the ircfs bus and the ircol bus must be pulled up globally with 330 resistors. (ircfs requires a precision resistor [1%].) 2 notes: 1. irena and irdat can be buffered between boards in multi-board configurations. where buffering is used, a 330 pull-up resistor can be used on each signal, on each board. where no buffering is used, the total impedance should be no less than 330 . 2. ircfs and ircol cannot be buffered. in multi-board configurations, the total impedance on ircol should be no smaller than 330 . ircfs should be pulled up only once, by a single 330 , 1% resistor. table 3. mode select and control signal descriptions plcc pqfp symbol i/o description 12 8 a/sync i backplane sync mode select. this pin selects the backplane sync mode. when this pin is left floating an internal pull-up defaults to the asynchronous mode (a/sync high). in the asynchronous mode 12 or more lxt914s can be connected on the backplane, and an external 10 mhz backplane clock source is not required. when the synchronous mode is selected (a/sync tied low), 32 or more lxt914s can be connected to the backplane and an external 10 mhz backplane clock source is required. 13 9 loc/ext i management mode select. this pin selects the management mode. when this pin is left floating, an internal pull-up defaults to the local management mode (loc/ext high). in the local mode, setup parameters are downloaded from an eeprom during initialization. once initialized with the setup parameters, the repeater functions independently. 28 33 ledjm/ auisel i/o led driver or dte/mau select. at reset, this pin selects the mode of the aui port. if left floating, an internal pull-down device forces the aui port to dte mode. if pulled high with an external resistor, the port changes to a mau, in which case the functions of the ledjm pin are disabled and the default led mode (refer to ta ble 7 ) is not available. ?30auiseli dte/mau select. this pin changes the mode of the aui port independent of the condition at reset. this function is available only in the 100-pin pqfp package. 17 35 14 40 ledm0 ledm1 i/o i/o led mode 0 & 1 select. these two pins select one of four possible led modes of operation. the functional description section describes the four modes.
intel ? lxt914 flexible quad ethernet repeater datasheet 31-oct-2005 intel ? lxt914 flexible quad ethernet repeater order number: 248989, revision: 003 11 table 4. serial port signal descriptions (external management mode) plcc pqfp symbol i/o description 14 11 seni i serial enable input. this active low input is used to access the lxt914 serial interface. to write to the serial input (sdi), an external management device (emd) must drive this pin from high to low. the input must be asserted low concurrent with the appearance of data on sdi and remain low for the duration of the serial input transaction. 15 12 seno o serial enable output. this active low output is used to access the serial interface of an emd. when the lxt914 sends a data stream to the emd through the serial port (sdo), this output transitions from high to low and remains low for the duration of the serial transmission. 16 13 sdi i serial data input. this pin is the input for the emd serial interface. setup and operating parameters are supplied to the lxt914 in a serial data stream through this port when operating in the external management mode. 17 14 sdo i/o serial data output. after each packet transmission or interrupt event, the lxt914 reports status information to the emd in a serial data stream through this port. 18 16 sclk i serial clock. this 10 mhz clock synchronizes the serial interface between the lxt914 and the emd. both devices must be supplied from the same clock source. in synchronous mode, sclk and bclk may be tied together. table 5. serial port signal descriptions (local management mode) plcc pqfp symbol i/o description 14 11 cs o chip select. the lxt914 is designed for use with an eeprom or similar device which may be used to store setup parameters and serially download them to the lxt914 during initialization. in a single-device application or in the first device of a daisy chain application, this pin is an active high chip select output used to enable the eeprom. seni i serial enable input. in subsequent devices of a daisy-chain configuration, a high-to-low transition on this pin enables the serial input port (sdi). the input must be asserted concurrent with the appearance of data on sdi and remain low for the duration of the serial input transaction. 15 12 seno o serial enable output. during initialization, the lxt914 accepts 48 bits of setup data through the sdi port. after the 48th bit, the lxt914 asserts this pin low. when multiple lxt914 devices are connected in a daisy-chain, this output is tied to the seni input of the next device in the chain. thus each device in the chain is serially enabled by the previous device until all the devices have read in their 48 bits of setup data. 16 13 sdi i setup data input. this pin is the serial input port for the setup parameters (48 bits).this pin should be tied low if no eeprom is present. 17 14 rts i/o request to send. in a single-device application or in the first device of a daisy chain application, this pin outputs a 9-bit, active high sequence. this pin must be tied to the eeprom di input to trigger the eeprom to download its stored data. in subsequent devices this pin is not used. 18 16 sclkio i/o serial clock. a 1 mhz clock provided by the first lxt914 in the chain to all subsequent repeaters and the eeprom. in the local mode all repeaters have their sclkio pins tied together.
intel ? lxt914 flexible quad ethernet repeater 31-oct-2005 datasheet intel ? lxt914 flexible quad ethernet repeater 12 order number: 248989, revision: 003 table 6. miscellaneous control signal descriptions plcc pqfp symbol i/o description 19 18 test i test mode select. this pin must be tied low for normal operation. 20 19 reset i reset. this pin resets the lxt914 circuitry when pulled high for 1 ms. 21 21 dsqe (local) i dsqe. in local mode, this pin controls the sqe function. when high, the sqe function of the aui port is disabled. when low, sqe is enabled. sectp1 (external) i security mode select (tp port 1). in external mode, this pin enables the security mode for twisted-pair port 1. when pulled high, the lxt914 jams the port. this pin must be tied low if external security control is not required. 22 23 24 22 23 24 sectp2 sectp3 sectp4 (external) i i i security mode select (tp ports 2?4). in external mode, these pins enable the security mode for the respective twisted-pair ports (tp1 through tp4). when pulled high, the lxt914 jams the affected port. the sec pins must be tied low if external security control is not required. 25 25 fps (local) i first position select. in the local mode this pin identifies the first device in a daisy chain configuration. when tied high (first position), the lxt914 controls the local eeprom by providing clock and handshaking. when tied low (not first), the lxt914 will accept clk and data in its turn from previous lxt914s in the data chain. secaui (external) i security mode select (aui port). in the external mode this pin enables the security mode for the aui port. when pulled high, the lxt914 jams the aui port. the security feature is available only in external management mode. table 7. led driver signal descriptions plcc pqfp symbol i/o description 27 32 ledcf o collision & fifo error led driver. this tri-state led driver pin reports collisions and fifo errors. it pulses low to report collisions, and pulses high to report fifo errors. when this pin is connected to the anode of one led and to the cathode of a second led, the lxt914 will simultaneously monitor and report both conditions independently. 28 33 ledjm o jabber/mjlp & manchester code violation led driver. this tri-state led driver pin reports jabber and code violations. it pulses low to report mau jabber lockup protection (mjlp), and pulses high to report manchester code violations. when this pin is connected to the anode of one led and to the cathode of a second led, the lxt914 will simultaneously monitor and report both conditions independently. 29 30 31 32 34 35 36 37 ledtp1 ledtp2 ledtp3 ledtp4 o o o o twisted-pair port led drivers. these tri-state led drivers use an alternating pulsed output to report tp port status. each pin should be tied to a pair of leds (to the anode of one led and the cathode of a second led). when connected this way, each pin reports five separate conditions (receive, transmit, link integrity, reverse polarity and auto partition). 33 38 ledaui o aui port led driver. this tri-state led driver uses an alternating pulsed output to report aui port status. this pin should be tied to a pair of leds (to the anode of one led and the cathode of a second led). when connected this way, this pin reports five separate conditions (receive, transmit, receive jabber, receive collision and auto partition.
intel ? lxt914 flexible quad ethernet repeater datasheet 31-oct-2005 intel ? lxt914 flexible quad ethernet repeater order number: 248989, revision: 003 13 table 8. repeater port signal descriptions plcc pqfp symbol i/o description 40 41 46 47 auidop auidon o o aui data outputs (positive and negative). these pins are the positive and negative data outputs for the aui port. in mau mode these pins are connected to the di pins of the dte. 42 43 48 49 auidip auidin i i aui data input (positive and negative). these pins are the positive and negative data inputs for the aui port. in mau mode, these pins are connected to the do pins of the dte. 44 45 54 55 auicip auicin i/o i/o aui collision (positive and negative). these pins are the positive and negative collision inputs for the aui port in dte mode. in mau mode, these pins output a collision indication to the dte. 56 57 54 53 50 51 48 47 71 72 68 67 63 64 60 59 tpdop1 tpdon1 tpdop2 tpdon2 tpdop3 tpdon3 tpdop4 tpdon4 o o o o o o o o twisted-pair data outputs (positive and negative). these pins are the positive (tpdop1-4) and negative (tpdon1-4) outputs to the network from the respective twisted-pair ports. 66 65 64 63 62 61 60 59 87 86 85 84 83 82 77 76 tpdip1 tpdin1 tpdip2 tpdin2 tpdip3 tpdin3 tpdip4 tpdin4 i i i i i i i i twisted-pair data inputs (positive and negative). these pins are the positive (tpdip1-4) and negative (tpdin1-4) inputs from the network to the respective twisted-pair ports.
intel ? lxt914 flexible quad ethernet repeater 31-oct-2005 datasheet intel ? lxt914 flexible quad ethernet repeater 14 order number: 248989, revision: 003 2.0 functional description 2.1 introduction the lxt914 repeater is an integrated hub repeater for 10base-t networks. the hub repeater is the central point for information transfer across the network. the lxt914 repeater offers multiple operating modes to suit a broad range of applications ranging from simple 4-port stand-alone hubs or attachments for print and file servers, up to intelligent 128-port enterprise systems with microprocessor/gate arlxt914 repeater ray management. the main functions of the lxt914 repeater hub repeater are data recovery and re-transmission and collision propagation. data packets received at the aui or 10base-t ports are detected and recovered by the port receivers before being passed to the repeater core circuitry for re-timing and re-transmission. data packets received through the irb port are essentially passed directly to the core for retransmission. after recovery of a valid data packet, the repeater broadcasts it to all enabled stations, except the originator station. 2.2 external interfaces the lxt914 repeater includes four 10base-t ports with internal filters. the lxt914 repeater also includes an attachment unit interface (aui) port, a serial port and an inter-repeater backplane (irb) port. the serial port allows an external device such as an eeprom to download setup parameters to the repeater. in more complex designs the serial port can also be used to monitor repeater status. the irb port enables multiple lxt914 repeater devices to be cascaded, creating a large, multi-port repeater. 2.2.1 10base-t ports the four 10base-t transceiver ports are completely self-contained. since the transmitters and receivers include the required filtering, only simple, inexpensive transformers are required to complete the 10base-t interface. each individual twisted-pair (tp) port is implemented in accordance with the ieee 802.3 10base-t standard. 2.2.2 aui port the aui port mode is selectable (dte mode or mau mode). with dte mode selected, the aui port allows connection of an external transceiver (10base2, 10base5, 10base-t or foirl) or a drop cable. with mau mode selected, the aui port establishes a mau output allowing direct connection to another dte interface. 2.2.3 serial port the serial port provides the management interface to the lxt914 repeater. refer to test specifications for serial port timing. the serial port can be either unidirectional or bidirectional, depending on the management mode selected. in the local management mode the serial port is
intel ? lxt914 flexible quad ethernet repeater datasheet 31-oct-2005 intel ? lxt914 flexible quad ethernet repeater order number: 248989, revision: 003 15 unidirectional (input only), and is used only to download setup parameters during initialization. the local mode is intended for use with a simple eeprom, but the serial port may be tied low if an eeprom is not required. in the external management mode, the serial port is bi-directional (input for setup parameters, output for status reports). the external mode is intended for use with an external management device (emd) and a media access controller (mac). the emd (typically a gate array) communicates with a microprocessor (e.g., intel 8051) and can control up to three lxt914 repeaters. this simplifies design of a relatively standard 12-port repeater on a single printed circuit board. 2.2.4 inter-repeater backplane the inter-repeater backplane (irb) allows several lxt914 repeaters to function as a single repeater. refer to test specifications for irb timing. the irb also allows several multi-repeater boards to be integrated in a standard rack and to function as a single unit. the irb supports ?hot swapping? for easy maintenance and troubleshooting. each individual repeater distributes recovered and re-timed data to other repeaters on the irb for broadcast on all ports simultaneously. this simultaneous rebroadcast allows the multi-repeater system to act as a single large repeater unit. the maximum number of repeaters on the irb is limited by bus loading factors such as parasitic capacitance. the irb can be operated synchronously or asynchronously. 2.2.4.1 synchronous irb operation in the synchronous mode, a common external source provides the 10 mhz backplane clock (bclkio) and the 20 mhz system clock (sysclk) to all repeaters. bclkio must be synchronous to sysclk and may be derived from sysclk using a divide-by-two circuit. in the synchronous mode 32 or more lxt914 repeaters may be connected on the irb, providing 128 10base-t ports and 32 aui ports. 2.2.4.2 asynchronous irb operation in the asynchronous mode an external bclkio source is not required. the repeaters run independently until one takes control of the irb. the transmitting repeater then outputs its own 10 mhz clock onto the bclkio line. all other repeaters sync to that clock for the duration of the transmission. in the asynchronous mode 12 or more lxt914 repeater may be connected to the irb, providing 48 10base-t ports and 12 aui ports. the maximum number of repeaters which may be linked on the backplane is limited by board design factors. the numbers listed above are engineering estimates only. stronger drivers and reduced capacitive loading in pcb layout may allow an increased device count. 2.3 internal repeater circuitry the basic repeater circuitry is shared among all the ports within the lxt914 repeater. it consists of a global repeater state machine, several timers and counters and the timing recovery circuit. the timing recovery circuit includes a fifo for re-timing and recovery of the clock which is used to clock the receive data out onto the irb.
intel ? lxt914 flexible quad ethernet repeater 31-oct-2005 datasheet intel ? lxt914 flexible quad ethernet repeater 16 order number: 248989, revision: 003 the shared functional blocks of the lxt914 repeater are controlled by the global state machine ( figure 3 ). this diagram and all associated notations used are in strict accordance with section 9.6 of the ieee 802.3 standard. the lxt914 repeater also implements the partition state diagram as defined by the ieee 802.3 standard and shown in figure 4 . the value of cclimit as implemented in the lxt914 repeater is 64. the cclimit value sets the number of consecutive collisions that must occur before the port is subjected to automatic partitioning. auto-partition/re-connection is also supported by the lxt914 repeater with tw5 conforming to the standard requirement of 450 to 560 bit times. 2.4 initialization the following description applies to the initial power-on reset and to any subsequent hardware reset. when a reset occurs (reset pin pulled high for > 1 ms), the device senses the levels at the various control pins (see figure 3 ) to determine the correct operating modes for management, leds, and the aui port functions. 2.4.1 local management mode initialization an internal pull-up causes the lxt914 repeater to default to the local management mode unless the loc/ext pin is tied low. in the local mode the serial port is a unidirectional interface used only to download setup parameters from an external device. in a locally managed multiple-repeater (daisy chain) configuration, the first repeater in the chain performs special functions. the first position select (fps) pin is used to establish position (fps high = first, fps low = not first). after establishing the hardware mode, each lxt914 repeater monitors the fps pin to determine its position. if fps is high (first position), the repeater performs the following functions: outputs a 1 mhz serial clock (sclk). sclk is derived from the 20 mhz sysclk input in async mode and from bclkio in sync mode; it is supplied to the sclk inputs of all other repeaters on the bus and to the eeprom. asserts chip select (cs) high to enable the eeprom. outputs a serial 9-bit request-to-send (rts) strobe. the programmable device responds to the rts strobe with a serial data stream containing the setup parameters for all repeaters in the chain. clocks the first 48 serial data input (sdi) bits from the eeprom into its setup register. refer to table 9 and table 10 for setup register bit assignments. asserts serial enable output (seno) low to enable the next repeater in line. the second repeater has fps tied low and serial enable input (seni) connected to the serial enable output (seno) of the first repeater. when enabled by a low on seni, each repeater downloads its portion of the stream, then stops accepting data and asserts seno low. the seno pin is linked to the seni input of the next repeater. this enables the next repeater to clock in its 48- bit word and so on. if fps is low (not first position), the repeater performs the following functions:
intel ? lxt914 flexible quad ethernet repeater datasheet 31-oct-2005 intel ? lxt914 flexible quad ethernet repeater order number: 248989, revision: 003 17 1. syncs to the 1 mhz serial clock (sclk) input. sclk is supplied by the first position repeater. 2. responds to seni low by enabling the sdi port. 3. clocks 48 bits from the eeprom into its setup register through the sdi port. 4. asserts seno low to enable the next repeater in line. figure 3. global state machine out (allxn) = preamble pattern send preamble pattern out (all) = idle idle begin start out (allxn) = twoones send tw o ones out (allxn) = data send data out (all) = jam transmit collision out (allxm) = jam one port left starttw1 out(all) = idle wait out (allxn) = jam receive collision power on uct collin(any) = sqe[n port(collin = sqe)] collin(anyxn) = sqe collin(anyxn) = sqe collin(n) = sqe + datain(n) = ii * collin(all) = sqe collin(anyxn) = sqe collin(anyxn) = sqe collin(anyxm) = sqe collin(any) = sqe + tw1done collin(only1) = sqe * tt(all) 96:[m port(collin = sqe)] datain(any) = ii * collin(all) = sqe:[n port(datain = ii)] tt(allxn) 62 * datardy * collin(all) = sqe * datain(n) = ii collin(n) = sqe + datain(n) = ii * collin(all) = sqe * alldatasent * tt(anayxn) < 96 collin(n) = sqe + datain = ii * collin(all) = sqe twoonessent * collin(all) = sqe * datain(n) = ii collin(all) = sqe * tt(all) 96 * tw2done datain(m) = ii* collin(all) = sqe* tw2done datain(n) = ii * collin(all) = sqe * tt(allxn) 96 * tw2done datain(n) = ii * collin(all) = sqe * tt(allxn) 96 * alldatasent
intel ? lxt914 flexible quad ethernet repeater 31-oct-2005 datasheet intel ? lxt914 flexible quad ethernet repeater 18 order number: 248989, revision: 003 figure 4. partitioning state machine partition wait datain(x) = ii collin(x) = sqe partition hold datain(x) = ii collin(x) = sqe dipresent(x) = ii *cipresent(x) = sqe dipresent(x) = ii + cipresent(x) = sqe cipresent(x) = sqe dipresent(x) = ii cipresent = sqe partition collision watch datain(x) = ii collin(x) = sqe starttw5 wait to restore port datain(x) = ii collin(x) = sqe cc(x) = 0 tw5done * dipresent(x) = ii * cipresent(x) = sqe count clear cc(x) = 0 datain(x) = dipresent(x) collin(x) = cipresent(x) begin collision count idle datain(x) = dipresent(x) collin(x) = cipresent(x) dipresent(x) = ii * cipresent(x) = sqe watch for collision starttw5 datain(x) = dipresent(x) collin(x) = cipresent(x) collsion count increment datain(x) = dipresent(x) collin(x) = cipresent(x) cc(x) = cc(x) + 1 starttw6 dipresent(x) = ii * cipresent(x) = sqe tw5done * dipresent(x) = ii * cipresent(x) = sqe dipresent(x) = ii + cipresent(x) = sqe cipresent(x) = sqe cc(x) cclimit + (tw6done * cipresent(x) = sqe) dipresent(x) = ii * cipresent(x) = sqe * cc(x) < cclimit * tw6done dipresent(x) = ii * cipresent (x) = sqe
intel ? lxt914 flexible quad ethernet repeater datasheet 31-oct-2005 intel ? lxt914 flexible quad ethernet repeater order number: 248989, revision: 003 19 2.4.2 external management mode initialization the lxt914 repeater operates in the external management mode when the loc/ext pin is tied low. in the external mode, the serial port is a bidirectional interface between the lxt914 repeater and an external management device (emd). the serial port is used to download initial setup parameters to the repeater and to monitor status reports from the repeater. the lxt914 repeater setup parameters can be changed at any time by the emd. the initialization process for each repeater in a managed mode configuration is the same, regardless of its position; each repeater is connected directly to the emd. each lxt914 repeater initializes as follows: 1. syncs to the 10 mhz serial clock (sclk) input. sclk must be supplied from an external source. 2. responds to seni low by enabling the sdi port. 3. clocks 48 bits from the emd into its setup register through the sdi port. 4. once initialized, the lxt914 repeater reports its status in a 48-bit serial stream after every packet transmission or interrupt event. refer to table 11 and table 12 for packet status register bit assignments and definitions. table 9. setup register bit assignments register d7 d6 d5 d4 d3 d2 d1 d0 sr(0) disli3 disli2 disli1 disap4 disap3 disap2 disap1 disapa sr(1) distx2 distx1 distxa dprc4 dprc3 dprc2 dprc1 disli4 sr(2) ersq1 disrx4 disrx3 disrx2 disrx1 disrxa distx4 distx3 sr(3) dfifoe dpfrm dsqe dmcv erxjab ersq4 ersq3 ersq2 sr(4) res res res res res res res res sr(5) res res res res res res res res table 10. setup register bit definitions bit definition disap x 1 = disable auto-partitioning on port x disli x 1 = disable link integrity on port x (twisted-pair ports only) dprc x 1 = disable polarity reverse detection and correction on port x (twisted-pair ports only) distx x 1 = disable transmit on port x disrx x 1 = disable receive on port x ersq x 1 = enable reduced squelch on port x (twisted-pair ports only) erxjab 1 = enable receive jab (long packet) (global) dmcv 1 = disable entering tx collision state on reception of manchester code violation dsqe 1 = disable signal quality error to provide heartbeat (aui port only) dpfrm 1 = disable end-of-frame checking for polarity correction (global) dfifoe 1 = disable entering tx collision state on fifo over/underflow condition (global) dmjlp 1 = disable mjlp counter (global) res reserved. must be set to 0.
intel ? lxt914 flexible quad ethernet repeater 31-oct-2005 datasheet intel ? lxt914 flexible quad ethernet repeater 20 order number: 248989, revision: 003 2.5 10base-t port operation 2.5.1 10base-t reception each lxt914 repeater 10base-t port receiver acquires data packets from its twisted-pair input (tpdip/tpdin). an internal rc filter and an intelligent squelch function discriminate noise from link test pulses and valid data streams. the receive function is activated only by valid data streams (above the squelch level and with proper timing). if the differential signal at the di circuit inputs falls below 75% of the threshold level (unsquelched) for eight bit times (typical), the port receiver enters the idle state. table 11. packet status register bit assignments register d7 d6 d5 d4 d3 d2 d1 d0 psr(0) col2 col1 cola rx4 rx3 rx2 rx1 rxa psr(1) pr2 pr1 lls4 lls3 lls2 lls1 col4 col3 psr(2) spa ap4 ap3 ap2 ap1 apa pr4 pr3 psr(3) lp3 lp2 lp1 lpa sp4 sp3 sp2 sp1 psr(4) rxjaba mjlp lcol4 lcol3 lcol2 lcol1 lcola lp4 psr(5) res rxcol mancv fifoer rxjab4 rxjab3 rxjab2 rxjab1 table 12. packet status register bit definitions bit 1 definition rx x received packet on twisted-pair port 1-4 or on aui port col x transmit collision of twisted -pair port 1-4 or on aui port llsc x link loss state on twisted-pair port 1-4 or on aui port pr x polarity reversed on twisted-pair port 1-4 or on aui port ap x auto-partition circuit isolated twisted-pair port 1-4 or the aui port sp x short packet (less than 74 bits) on twisted-pair port 1-4 or on aui port lp x long packet (more than 1.3 ms) on twisted-pair port 1-4 or on aui port lcol x late collision on twisted-pair port 1-4 or on aui port mjlp mau jabber lockup protection rxjab x receive jabber lockup protection fifoer fifo overflow/underflow mancv manchester code violation rxcol receive collision on the aui port res reserved. not used note: 1. the notation abcd x means bit abcd associated with port x , which can be any of the four twisted- pair ports or the aui port.
intel ? lxt914 flexible quad ethernet repeater datasheet 31-oct-2005 intel ? lxt914 flexible quad ethernet repeater order number: 248989, revision: 003 21 2.5.1.1 programmable internal squelch level the 10base-t port receivers have two squelch levels: a normal level or default setting and a reduced level squelch (-4.5 db) selected when the ersqx is set in the setup register. when used with low noise media such as shielded twisted-pair cabling, the reduced squelch level allows longer loop lengths in the network. 2.5.1.2 polarity detection and correction the lxt914 repeater 10base-t ports detect and correct for reversed polarity by monitoring link pulses and end-of-frame sequences. a reversed polarity condition is declared when the port receives sixteen or more incorrect link pulses consecutively, or four frames with reversed start-of- idle sequence. in these cases the receiver reverses the polarity of the signal and thereby corrects for this failure condition. if the port enters the link fail state and no valid data or link pulses are received within 96 to 128 ms, the polarity is reset to the default non-flipped condition. (if link integrity testing is disabled, polarity detection is based only on received data.) 2.5.2 10base-t transmission each lxt914 repeater 10base-t port receives nrz data from the repeater core and passes it through a manchester encoder. the encoded data is then transmitted to the twisted-pair network (the do circuit). the advanced integrated pulse shaping and filtering network produces the pre- distorted and pre-filtered output signal to meet the 10base-t jitter template. an internal continuous resistor-capacitor filter is used to remove any high-frequency clocking noise from the pulse shaping circuitry. integrated filters simplify the design work required for fcc compliant emi performance. during idle periods, the lxt914 repeater 10base-t ports transmit link integrity test pulses in accordance with the 802.3 10base-t standard. data packets transmitted by the lxt914 repeater contain a minimum of 56 preamble bits before the start of frame delimiter (sfd). in the asynchronous mode, preamble regeneration takes place on the transmit side. in the synchronous mode, the preamble is regenerated on the receive side and distributed via the irb. if the total packet is less than 96 bits including the preamble, the lxt914 repeater extends the packet length to 96 bits by appending a jam signal (1010...) at the end. 2.5.3 10base-t link integrity testing the lxt914 repeater fully supports the 10base-t link integrity test function. the link integrity test determines the status of the receive side twisted-pair cable. link integrity testing is enabled unless disabled via the dislix bit in the setup register. when enabled, the receiver recognizes link integrity pulses transmitted in the absence of data traffic. with no data packets or link integrity pulses within 100 (50) ms, the port enters a link fail state and disables its transmitter. the port remains in the link fail state until it detects three or more data packets or link integrity pulses.
intel ? lxt914 flexible quad ethernet repeater 31-oct-2005 datasheet intel ? lxt914 flexible quad ethernet repeater 22 order number: 248989, revision: 003 2.6 aui port operation 2.6.1 aui reception the lxt914 repeater aui port receiver acquires data packets from the network (auidip/ auidin). only valid data streams above the squelch level activate the receive function. if the differential signal at the di circuit inputs falls below 75% of the threshold level (unsquelched) for 8 bit times (typical), the aui receiver enters the idle state. 2.6.2 aui transmission the lxt914 repeater aui port receives nrz data from the repeater core, and passes it through a manchester encoder. the encoded data then goes out on the network (auidop/auidon). 2.6.3 aui mode selection (dte/mau) the lxt914 repeater allows the user to change the mode of the aui from a dte to a mau interface. this option is available on both 68- and 100-pin versions except as follows: ? when using the ledjm/auisel pin to select the aui interface mode the following is true: after reset the state of the ledjm/auisel pin is sensed for the correct mode. the ledjm/ auisel pin when floated or pulled low will select the dte interface and the ledjm/ auisel output is still available. when the ledjm/auisel pin is pulled high the mau interface is selected and the ledjm/auisel function is unavailable. ? the 100-pin pqfp has an additional pin, auisel (pin 30). when using this pin to select the aui interface mode the ledjm/auisel pin is still a functional led driver. the auisel pin is not latched after reset and is actively polled to determine which aui interface mode is to be used. refer to table 13 . table 13. aui mode selection (dte/mau) app # auisel (pqfp only ) ledjm/ auisel (both pkgs) aui mode available led modes 1 low low dte default, 0-3 2low high mau1-3 3 high low mau default, 0-3 4 high high mau 1-3 note: application 3 is valid only when using the 100-pin pqfp.
intel ? lxt914 flexible quad ethernet repeater datasheet 31-oct-2005 intel ? lxt914 flexible quad ethernet repeater order number: 248989, revision: 003 23 2.7 collision handling a collision occurs when two or more repeater ports receive simultaneously, or when the aui cip/ cin signal is active. the lxt914 repeater fully complies with the ieee 802.3 collision specifications, both in individual and multi-repeater applications. in multiple-repeater configurations, collision signaling on the irb allows all repeaters to share collision parameters, acting as a single large repeater. ircol is a digital open-drain pin. ircfs is an analog/digital port. the ircol and ircfs lines are pulled up globally (i.e., each signal requires one pull-up resistor for all boards). if there are eight 3-repeater boards in the system, all eight boards share a single pull-up resistor for ircol and a single pull-up resistor for ircfs . the global pull-up may be located on one of the boards, or on the backplane. the ircfs line requires a precision ( 1%) resistor. the irena , irdat and irden lines are each pulled up locally (one pull-up resistor per board) if external bus drivers are used. if no bus drivers are used then only one global pull-up per signal is used. 2.8 security mode the lxt914 repeater security mode is fully transparent to the user. in the external management mode, the security feature is available for all four tp ports and the aui port. in the local mode, security is available for the tp ports only (the secaui input is reassigned as fps). the security inputs are normally held low to disable the security feature. any input can independently be pulled high to scramble the respective port for any given length of time. for applications which do not require security control, the sec pins must be tied low. the security mode pins are real time response inputs. this allows the board designer to screen the destination address with an application specific device and (on match of the destination address) to assert the security input to jam the respective port for the given frame. this real time detection and jam assertion method provides the flexibility to implement customer specific solutions. the destination address decoding and security signal assertion functions can be integrated into the external management device. 2.9 led display the led display interface consists of seven integrated led drivers, one for each of the five network ports and two for common functions. each pin provides a three-state pulsed output (+5 v, high z, and 0 v) which allows multiple conditions to be monitored and reported independently. table 14 shows the led mode selected with each ledm1 and ledm0 combination. figure 5 shows the led driver output conditions, and table 15 through table 18 list the repeater states associated with each of the five conditions. note: if led mode 0 is selected and the ledjm/auisel pin is high (which selects mau mode), the device defaults to led mode 1. led mode 0 is not available when ledjm/auisel is pulled high.
intel ? lxt914 flexible quad ethernet repeater 31-oct-2005 datasheet intel ? lxt914 flexible quad ethernet repeater 24 order number: 248989, revision: 003 led mode 0 (default) this mode is selected when ledm1 and ledm0 are floating or pulled low. refer to table 15 . this mode is not available when using the ledjm/auisel pin to select a mau interface in the aui port. in this case, the led mode defaults to mode 1. led mode 1 this mode is selected when ledm1 is floating or pulled low and ledm0 is pulled high by a pull-up resistor. refer to table 16 . led mode 2 this mode is selected when ledm1 is pulled high by a pull-up resistor and ledm0 is floating or pulled low. refer to table 17 . led mode 3. this mode is selected when ledm1 is pulled high by a pull-up resistor and ledm0 is also pulled high by a pull-up resistor. refer to table 18 . table 14. led mode selection ledm1 ledm0 led mode selected plcc pin 35 17 pqfp pin 40 14 low low 0 note 1 low high 1 high low 2 high high 3 note: 1. this mode is not available when using the ledjm/auisel pin to select a mau interface in the aui port. in this case, the led mode defaults to led mode 1. table 15. mode 0 (default) led truth table condition ledtp 1?4 ledaui ledcf ledjm 1 rx link pulse n/a fifo error manchester code violation 2 tx packet tx packet n/a n/a 3 reversed polarity n/a collision mau jabber lockup protection (mjlp) 4 rx packet rx packet n/a n/a 5 partitioned out partitioned out n/a n/a table 16. mode 1 led truth table condition ledtp 1?4 ledaui ledcf ledjm 1 rx link pulse n/a mau jabber lockup protection (mjlp) n/a 2 n/a n/a n/a n/a 3 n/a n/a collision n/a 4 rx packet rx packet n/a n/a 5 n/a n/a n/a n/a
intel ? lxt914 flexible quad ethernet repeater datasheet 31-oct-2005 intel ? lxt914 flexible quad ethernet repeater order number: 248989, revision: 003 25 table 17. mode 2 led truth table condition ledtp 1?4 ledaui ledcf ledjm 1 rx link pulse n/a mau jabber lockup protection (mjlp) n/a 2 partitioned out partitioned out n/a n/a 3 n/a n/a collision n/a 4 rx packet rx packet n/a n/a 5 n/a n/a n/a n/a table 18. mode 3 led truth table condition ledtp 1?4 ledaui ledcf ledjm 1 rx link pulse n/a mau jabber lockup protection (mjlp) n/a 2 rx packet rx packet n/a n/a 3 partitioned out partitioned out collision n/a 4 n/a n/a n/a n/a 5 n/a n/a n/a n/a
intel ? lxt914 flexible quad ethernet repeater 31-oct-2005 datasheet intel ? lxt914 flexible quad ethernet repeater 26 order number: 248989, revision: 003 figure 5. integrated led driver indications 4 ms 4 ms 4 ms 4 ms 4 ms 4 ms 4 ms 4 ms condition 4: blinking red 256 ms 256 ms +5v high z 0v (gnd) 4 ms 4 ms 4 ms 4 ms 4 ms 4 ms +5v high z 0v (gnd) condition 3: steady red +5v high z 0v (gnd) 4 ms 4 ms 4 ms 4 ms 4 ms 4 ms 4 ms condition 2: blinking green 256 ms 256 ms 4 ms 4 ms 4 ms 4 ms 4 ms 4 ms +5v high z 0v (gnd) 4 ms condition 1: steady green 0v (gnd) 4 ms 4 ms 4 ms 93.75 ms +5v high z 4 ms 4 ms 5.33 hz 4 ms 4 ms condition 5: alternating red/green red green 820 820 470 lxt914 led driver +5 v red green 330 330 70 lxt914 led driver +5 v 2 ma operation 5 ma operation
intel ? lxt914 flexible quad ethernet repeater datasheet 31-oct-2005 intel ? lxt914 flexible quad ethernet repeater order number: 248989, revision: 003 27 3.0 application information 3.1 layout requirements 3.1.1 the twisted pair interface the four, twisted-pair output circuits are identical. each tpdop/tpdon signal has a 24.9 , 1%, series resistor and a 120pf capacitor differentially across the positive and negative outputs. these signals go directly to a 1: 2 transformer creating the necessary 100 termination for the cable. the tpdip/tpdin signals have a 100 resistor across the positive and negative input signals to terminate the 100 signal received from the line. to calculate the impedance on the output line interface, use: (24.9 + 24.9 ) * 2 2 100 . the layout of the twisted-pair ports is critical in complex designs. run the signals directly from the device to the discrete termination components (located close to the transformers). the signals running from the transformers to the connector should run in close pairs directly to the connector. be careful not to cross the transmit and receive pairs. one way to avoid a problem is to run the receive pairs on the component side and the transmit pairs on the solder side. careful planning during the schematic and layout stages can avoid these problems. the pcb layout should have no ground or power planes from the transformers to the connectors. the data signals should be the only traces in this area. place the chassis ground for the connectors near the edge of the pcb, away from the signals, connecting the connector shield with the chassis. 3.1.2 the rbias pin the rbias signal sets the levels for the output drivers of the lxt914 repeater. any emissions or common mode noise entering the device here could be measured on the twisted pair output signals. the lxt914 repeater requires a 12.4 k , 1% resistor directly connected to rbias. this connection should be as short as possible. the ground rails from the adjacent ground pins should come directly off of the device to enclose the resistor and pin forming a shielded area between the rbias connection and the switching signals on the pcb. 3.2 12-port hub repeater figure 6 through figure 9 (sheets 1 through 4) show a simple 12-port hub repeater application with three lxt914 repeaters. this application also provides two additional aui ports?one db-15 connector and one coaxial port. the application shown uses the asynchronous backplane mode so no external backplane clock source is required. figure 6 (sheet 1) shows the xl93c46 eeprom which downloads the setup parameters for all the lxt914 repeater devices at initialization. (this eeprom could be replaced with a simple pull down resistor on the sdi pin. this will select the default conditions of the set up register.) a single 20 mhz crystal provides the sysclk for all three lxt914 repeater. the lxt914 repeater hub repeater on sheet 1 provides the aui db-15 connector as well as four twisted-pair ports. table 19 lists transformers suggested for use with the lxt914 repeater.
intel ? lxt914 flexible quad ethernet repeater 31-oct-2005 datasheet intel ? lxt914 flexible quad ethernet repeater 28 order number: 248989, revision: 003 figure 7 (sheet 2) shows a second lxt914 repeater hub repeater with four tp ports and a coaxial port. the md-001 coax transceiver is used to implement the port. figure 8 (sheet 3) shows the third lxt914 repeater device with its four tp ports and indicator leds. the aui port of the third lxt914 repeater is not used. figure 9 (sheet 4) of the schematic shows the leds for the remaining lxt914 repeaters, along with the led operation table. 3.3 8-port print or file server figure 10 and figure 11 (sheets 1 and 2) show an eight-port repeater attachment for an existing single port aui or 10base5 interface. this application can be added to a current design with an existing aui or 10base5 interface. this circuit allows increased connectivity without the need for another external remote hub. the application shown is a 68-pin plcc, an asynchronous backplane with both lxt914 repeaters in the first position. in figure 10 (sheet 1) the lxt914 repeater is set up with the leds in mode 1 with one led per port and a single collision led. the twisted pair port leds display link integrity only. (refer to table 16 .) led mode 1 is selected by pulling ledm0 high with a 1 k resistor on pin 17 and pulling ledm1 low with pin 35 attached to ground. figure 11 (sheet 2) has the same configuration, mode of operation and led mode as used in sheet 1. however, the aui port has been configured as a mau interface. this is selected when ledjm/ auisel on pin 28 is pulled up through a 1 k resistor. this mode disables the ledjm pin as an led driver. (see table 13 .) the mau interface now configured on the lxt914 repeater allows the aui port to attach to a dte interface. this application increases connectivity to any existing single-port ethernet design. this unique application allows the designer to integrate an external hub, eliminating the need for additional external equipment. table 19. manufacturers magnetics list manufacturer quad transmit quad receive tx/rx pairs bell fuse s553-5999-02 s553-5999-03 ? fil-mag 23z339 23z338 ? halo (octal) td54-1006l1 tg54-1006n2 td01-1006l1 tg01-1006n2 td42-2006q; td43-2006k; tg42-1406n1 tg43-1406n ? ? tg44-s010nx kappa tp4003p tp497p101 ? nanopulse 5976 5977 ? pca epe6009 epe6010 ? pulse eng. pe68810 pe68820 pe65745; pe65994; pe65746; pe65998 valor pt4116 pt4117 pt4069n1; pt4068n1; st7011s2; st7010s2
intel ? lxt914 flexible quad ethernet repeater datasheet 31-oct-2005 intel ? lxt914 flexible quad ethernet repeater order number: 248989, revision: 003 29 figure 6. 12-port application schematic, 68-pin plcc package (sheet 1 of 4)
intel ? lxt914 flexible quad ethernet repeater 31-oct-2005 datasheet intel ? lxt914 flexible quad ethernet repeater 30 order number: 248989, revision: 003 figure 7. 12-port application schematic, 68-pin plcc package (sheet 2 of 4)
intel ? lxt914 flexible quad ethernet repeater datasheet 31-oct-2005 intel ? lxt914 flexible quad ethernet repeater order number: 248989, revision: 003 31 figure 8. 12-port application schematic, 68-pin plcc package (sheet 3 of 4)
intel ? lxt914 flexible quad ethernet repeater 31-oct-2005 datasheet intel ? lxt914 flexible quad ethernet repeater 32 order number: 248989, revision: 003 figure 9. 12-port application schematic, 68-pin plcc package (sheet 4 of 4)
intel ? lxt914 flexible quad ethernet repeater datasheet 31-oct-2005 intel ? lxt914 flexible quad ethernet repeater order number: 248989, revision: 003 33 figure 10. 8-port application schematic, led mode 1 with auisel = mau (sheet 1 of 2)
intel ? lxt914 flexible quad ethernet repeater 31-oct-2005 datasheet intel ? lxt914 flexible quad ethernet repeater 34 order number: 248989, revision: 003 figure 11. 8-port application schematic, led mode 1 with auisel = mau (sheet 2 of 2)
intel ? lxt914 flexible quad ethernet repeater datasheet 31-oct-2005 intel ? lxt914 flexible quad ethernet repeater order number: 248989, revision: 003 35 4.0 test specifications note: table 20 through table 28 and figure 12 and figure 13 represent the performance specifications of the lxt914. these specifications are guaranteed by test except where noted ?by design.? minimum and maximum values listed in table 22 through table 28 apply over the recommended operating conditions specified in table 21 . table 20. absolute maximum ratings parameter symbol min typ max units supply voltage v cc -0.3 ? 6 v operating temperature lxt914pc/qc t op 0?+70 c lxt914pe t op -40 ? +85 c storage temperature t st -65 ? +150 c caution: exceeding these values may cause permanent damage. functional operation under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 21. recommended operating conditions parameter symbol min typ max units recommended supply voltage v cc 4.75 5.0 5.25 v recommended operating temperature lxt914pc/qc t op 0?+70 c lxt914pe t op -40 ? +85 c table 22. i/o electrical characteristics 1 (sheet 1 of 2) parameter symbol min typ 2 max units test conditions supply current i cc ??240ma100 test load, no leds input low voltage v il ??0.8v? input low voltage (reset) v ilreset ??0.8vv cc = 5.25 v input high voltage v ih 2.0 ? ? v ? input high voltage (reset) v ihreset 4.0 ? ? v v cc = 4.75 v output low voltage v ol ??0.4vi ol = 1.6 ma output low voltage v ol ??10% v cc i ol < 10 a output low voltage (led) v oll ??1.0vi oll = 5 ma output high voltage v oh 2.4 ? ? v i oh = 40 a output high voltage v oh 90 ? ? % v cc i oh < 10 a output high voltage (led) v ohl 4??vi ohl = -5 ma notes: 1. not applicable to irb signals. irb electrical characteristics are specified in table 25 . 2. typical values are at 25 c and are for design aid only; they are not guaranteed and not subject to production testing. 3. supply current may vary depending on the transformer, led, and resistor selections.
intel ? lxt914 flexible quad ethernet repeater 31-oct-2005 datasheet intel ? lxt914 flexible quad ethernet repeater 36 order number: 248989, revision: 003 input low current i il ??2mav ol = .4 v output rise / fall time ? ? 3 8 ns c load = 20 pf reset pulse width pw rese t 1.0 ? ? ms v cc = 4.75 v reset fall time tf reset ??20.0 sv ihreset to v ilreset table 23. aui electrical characteristics parameter symbol min typ 1 max units test conditions input low current i il ??-700 a input high current i ih ??500 a differential output voltage v od 550 ? 1200 mv receive input impedance z in ?20?k between cip/cin & dip/ din differential squelch threshold v ds ?220?mv note: 1. typical values are at 25 c and are for design aid only; they are not guaranteed and not subject to production testing. table 24. twisted-pair electrical characteristics parameter symbol min typ 1 max units test conditions transmit output impedance z out ?5? peak differential output voltage v od 3.3 3.5 3.7 v load = 100 at tpop and tpon transmit timing jitter addition ? ? 6.4 10 ns 0 line length transmit timing jitter added by the mau and pls sections 2 ? ? 3.5 5.5 ns after line model specified by ieee 802.3 for 10base-t receive input impedance z in ?20?k between tpip/tpin differential squelch threshold (normal threshold: ersq x = 0) v ds 300 420 565 mv 5 mhz square wave input differential squelch threshold (reduced threshold: ersq x = 1) v dsl 180 250 345 mv 5 mhz square wave input notes: 1. typical values are at 25 c and are for design aid only; they are not guaranteed and not subject to production testing. 2. ieee 802.3 specifies maximum jitter additions at 1.5 ns for the aui cable, 0.5 ns from the encoder, and 3.5 ns from the mau. table 22. i/o electrical characteristics 1 (sheet 2 of 2) parameter symbol min typ 2 max units test conditions notes: 1. not applicable to irb signals. irb electrical characteristics are specified in table 25 . 2. typical values are at 25 c and are for design aid only; they are not guaranteed and not subject to production testing. 3. supply current may vary depending on the transformer, led, and resistor selections.
intel ? lxt914 flexible quad ethernet repeater datasheet 31-oct-2005 intel ? lxt914 flexible quad ethernet repeater order number: 248989, revision: 003 37 table 25. irb electrical characteristics parameter symbol min typ 1 max units test conditions output low voltage v ol ?.3.6v output rise or fall time t f ? 4 12 ns input low voltage: irena , ircol & irdat v ilirb ??0.8vr l = 330 input high voltage: irena , ircol & irdat v ihirb 3.0 ? ? v r l = 330 input low voltage: bclkio v ilbclk ??0.4vr l = 330 input high voltage: bclkio v ihbclk 4.0 ? ? v r l = 330 note: 1. typical values are at 25 c and are for design aid only; they are not guaranteed and not subject to production testing. table 26. switching characteristics parameter min typ 1 max units jabber timing maximum transmit time 5.0 ? 5.5 ms unjab time ? 9.6 ? s link integrity timing time link loss ?60?ms time between link integrity pulses 10 ? 20 ms interval for valid receive link integrity pulses 4.1 ? 30 ms note: 1. typical values are at 25 c and are for design aid only; they are not guaranteed and not subject to production testing. table 27. serial port timing?external mode parameter symbol minimum typical 1 maximum units sclkio high to seni low (active) ts1 0 ? 50 ns sclkio high to sdin data valid ts2 0 ? 50 ns sclkio high to seno low (active) ts3 5 ? 15 ns sclkio low to sdout data valid ts4 5 ? 15 ns note: 1. typical values are at 25 c and are for design aid only; they are not guaranteed and not subject to production testing.
intel ? lxt914 flexible quad ethernet repeater 31-oct-2005 datasheet intel ? lxt914 flexible quad ethernet repeater 38 order number: 248989, revision: 003 figure 12. serial port timing table 28. inter-repeater bus timing parameter symbol minimum typical 1 maximum units start of frame to irden low (active) tirb1 10 ? 150 ns start of frame to irena low (active) tirb2 125 ? 225 ns bclkio to irdat valid (synchronous mode) tirb3 5 ? 30 ns bclkio to irdat valid (asynchronous mode) tirb3 ? 50 ? ns irena low (active) to tp outputs active tirb4 525 ? 600 ns irena low (active) to aui output active tirb5 475 ? 525 ns end of frame clock to irena high (inactive) tirb6 5 ? 30 ns irena high (inactive) to irden high (inactive) tirb7 95 ? 105 ns irena high (inactive) to tp outputs inactive tirb8 575 ? 600 ns irena high (inactive) to aui output inactive tirb9 425 ? 450 ns note: 1. typical values are at 25 c and are for design aid only; they are not guaranteed and not subject to production testing. 123456 48 sclkio reset seni sdin seno sdout t s1 t s2 t s3 t s4
intel ? lxt914 flexible quad ethernet repeater datasheet 31-oct-2005 intel ? lxt914 flexible quad ethernet repeater order number: 248989, revision: 003 39 figure 13. inter-repeater bus timing t irb8 t irb4 t irb5 t irb9 t irb7 t irb2 t irb1 t irb6 t irb3 bclkio irdat irena irden aui tps rx data
intel ? lxt914 flexible quad ethernet repeater 31-oct-2005 datasheet intel ? lxt914 flexible quad ethernet repeater 40 order number: 248989, revision: 003 5.0 package specifications figure 14. lxt914pc/pe package specifications dim inches millimet ers min max min max a 0.165 0.180 4.191 4.572 a1 0.090 0.120 2.286 3.048 a2 0.062 0.083 1.575 2.108 b0.050? 1.270? c 0.026 0.032 0.660 0.813 d 0.985 0.995 25.019 25.273 d1 0.950 0.958 24.130 24.333 f 0.013 0.021 0.330 0.533 68-pin plastic leaded chip carrier part number lxt914pc for commercial temperature range (0 c to +70 c) part number lxt914pe for extended temperature range (-40 c to +85 c)
intel ? lxt914 flexible quad ethernet repeater datasheet 31-oct-2005 intel ? lxt914 flexible quad ethernet repeater order number: 248989, revision: 003 41 figure 15. lxt914qc package specifications d side pi n count = 30 e side pin count = 20 dim inches millimeters min max min max a ? 0.134 ? 3.40 a1 0.010 ? 0.25 ? a2 0.100 0.120 2.55 3.05 b 0.009 0.015 0.22 0.38 d 0.931 0.951 23.65 24.15 d1 0.783 0.791 19.90 20.10 d3 0.742 ref 18.85 ref e 0.695 0.715 17.65 18.15 e1 0.547 0.555 13.90 14.10 e3 0.486 ref 12.35 ref e (nominal) 0.026 bsc 1 (nominal) 0.65 bsc 1 l 0.026 0.037 0.65 0.95 l1 0.077 ref 1.95 ref q0 70 7 q3 5 16 5 16 1. bsc = basic spacing between centers 100-pin quad flat package part number lxt914q c commercial temperature range (0 c to +70 c)
intel ? lxt914 flexible quad ethernet repeater 31-oct-2005 datasheet intel ? lxt914 flexible quad ethernet repeater 42 order number: 248989, revision: 003 5.1 top-label marking figure 16 shows a sample plcc package for the lxt914 repeater. note: in contrast to the pb-free (rohs-compliant) plcc packages, the non-rohs-compliant packages do not have the ?e3? symbol in the last line of the package label. figure 17 shows a sample pb-free (rohs-compliant) plcc package for the lxt914 repeater. figure 16. sample plcc package - intel ? lxt914 repeater p in 1 lxt914pc b3 xxxxxxxx part number fpo number bsmc bottom side mark cod e b5388-01 figure 17. sample pb-free (rohs-compliant) plcc package - intel ? lxt914 repeater pin 1 eelxt914c b3 xxxxxxxx part number fpo number e3 pb-free indication bsmc bottom side mark code b5389-01
intel ? lxt914 flexible quad ethernet repeater datasheet 31-oct-2005 intel ? lxt914 flexible quad ethernet repeater order number: 248989, revision: 003 43 figure 18 shows a sample pqfp package for the lxt914 repeater. note: in contrast to the pb-free (rohs-compliant) pqfp packages, the non-rohs-compliant packages do not have the ?e3? symbol in the last line of the package label. figure 19 shows a sample pb-free (rohs-compliant) pqfp package for the lxt914 repeater. figure 18. sample pqfp package - intel ? lxt914 repeater pin 1 lxt914qc b3 xxxxxxxx part number fpo number bsmc bottom side mark cod e b5390-01 figure 19. sample pb-free (rohs-compliant) pqfp package - intel ? lxt914 repeater pin 1 eglxt914c b3 xxxxxxxx part number fpo number e3 pb-free indication bsmc bottom side mark code b5391-01
intel ? lxt914 flexible quad ethernet repeater 31-oct-2005 datasheet intel ? lxt914 flexible quad ethernet repeater 44 order number: 248989, revision: 003 6.0 product ordering information figure 29 and figure 20 provide ixf1110 mac product ordering information. table 29. product ordering information number revision package type pin count rohs compliant nlxt914pc.b3 b3 plcc 68 no eelxt914pc.b3 b3 plcc 68 yes nlxt914pe.b3 b3 plcc 68 no eelxt914pe.b3 b3 plcc 68 yes slxt914qc.b3 b3 pqfp 100 no eglxt914qc.b3 b3 pqfp 100 yes
intel ? lxt914 flexible quad ethernet repeater datasheet 31-oct-2005 intel ? lxt914 flexible quad ethernet repeater order number: 248989, revision: 003 45 figure 20. ordering information matrix ? sample nc 914 p lxt b3 product revision xn = 2 alphanumeric characters temperature range a = ambient (0 ? 55 0 c) c = commercial (0 ? 70 0 c) e = extended (-40 ? 85 0 c) internal package designator l = lqfp p = plcc n = dip q = pqfp h = qfp t = tqfp b = bga c = cbga e = tbga k = hsbga (bga with heat slug product code xxxxx = 3-5 digit alphanumeric ixa product prefix lxt = phy layer device ixe = switching engine ixf = formatting device (mac/framer) ixp = network processor intel package designator b5360-01

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